There exists a continuing requirement to improve semiconductor device performance and scale down semiconductor devices. As the size reduces, the performance requirements become more stringent. A characteristic that limits scalability and device performance is electron and/or hole mobility throughout the channel region of transistors. Another characteristic that limits scalability and device performance is the total resistance of transistors. For example, the current performance of devices is highly relative to the total resistances and mobility of carriers.
One technique that may improve scaling limits and device performance is to introduce strain into the channel region, which can improve electron and/or hole mobility. Different types of strain, including expansive strain, uniaxial tensile strain, and compressive strain, have been introduced into channel regions of various types of transistors in order to determine their effect on electron and/or hole mobility.
One technique that may improve scaling limits and device performance is to reduce the contact resistance. In 45 nm technology and below, the external resistance REXT dominates the performance of the device drive currents. In addition, it is found that contact resistance holds a majority of the external resistance REXT. High contact resistance causes the device drive currents to reduce. However, there is no optimized profile of a source/drain region that is able to reduce contact resistance and at the same time not influence the strain in the channel region. In order to obtain higher drive currents and a more efficient performance, a new profile of a source/drain region is required.